Single transistor vertical memory gain cell

ABSTRACT

A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following co-pending, commonlyassigned U.S. patent application: “Merged MOS-Bipolar Capacitor MemoryCell,” Ser. No. 10/230,929, which is filed on even date herewith andwhich disclosure is herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and inparticular to a single transistor vertical memory gain cell.

BACKGROUND OF THE INVENTION

An essential semiconductor device is semiconductor memory, such as arandom access memory (RAM) device. A RAM device allows the user toexecute both read and write operations on its memory cells. Typicalexamples of RAM devices include dynamic random access memory (DRAM) andstatic random access memory (SRAM).

DRAM is a specific category of RAM containing an array of individualmemory cells, where each cell includes a capacitor for holding a chargeand a transistor for accessing the charge held in the capacitor. Thetransistor is often referred to as the access transistor or the transferdevice of the DRAM cell.

FIG. 1 illustrates a portion of a DRAM memory circuit containing twoneighboring DRAM cells 100. Each cell 100 contains a storage capacitor140 and an access field effect transistor or transfer device 120. Foreach cell, one side of the storage capacitor 140 is connected to areference voltage (illustrated as a ground potential for conveniencepurposes). The other side of the storage capacitor 140 is connected tothe drain of the transfer device 120. The gate of the transfer device120 is connected to a signal known in the art as a word line 180. Thesource of the transfer device 120 is connected to a signal known in theart as a bit line 160 (also known in the art as a digit line). With thememory cell 100 components connected in this manner, it is apparent thatthe word line 180 controls access to the storage capacitor 140 byallowing or preventing the signal (representing a logic “0” or a logic“1”) carried on the bit line 160 to be written to or read from thestorage capacitor 140. Thus, each cell 100 contains one bit of data(i.e., a logic “0” or logic “1”).

In FIG. 2 a DRAM circuit 240 is illustrated. The DRAM 240 contains amemory array 242, row and column decoders 244, 248 and a sense amplifiercircuit 246. The memory array 242 consists of a plurality of memorycells 200 (constructed as illustrated in FIG. 1) whose word lines 280and bit lines 260 are commonly arranged into rows and columns,respectively. The bit lines 260 of the memory array 242 are connected tothe sense amplifier circuit 246, while its word lines 280 are connectedto the row decoder 244. Address and control signals are input onaddress/control lines 261 into the DRAM 240 and connected to the columndecoder 248, sense amplifier circuit 246 and row decoder 244 and areused to gain read and write access, among other things, to the memoryarray 242.

The column decoder 248 is connected to the sense amplifier circuit 246via control and column select signals on column select lines 262. Thesense amplifier circuit 246 receives input data destined for the memoryarray 242 and outputs data read from the memory array 242 overinput/output (I/O) data lines 263. Data is read from the cells of thememory array 242 by activating a word line 280 (via the row decoder244), which couples all of the memory cells corresponding to that wordline to respective bit lines 260, which define the columns of the array.One or more bit lines 260 are also activated. When a particular wordline 280 and bit lines 260 are activated, the sense amplifier circuit246 connected to a bit line column detects and amplifies the data bittransferred from the storage capacitor of the memory cell to its bitline 260 by measuring the potential difference between the activated bitline 260 and a reference line which may be an inactive bit line. Theoperation of DRAM sense amplifiers is described, for example, in U.S.Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to MicronTechnology Inc., and incorporated by reference herein.

The memory cells of dynamic random access memories (DRAMs) are comprisedof two main components, a field-effect transistor (FET) and a capacitorwhich functions as a storage element. The need to increase the storagecapability of semiconductor memory devices has led to the development ofvery large scale integrated (VLSI) cells which provides a substantialincrease in component density. As component density has increased, cellcapacitance has had to be decreased because of the need to maintainisolation between adjacent devices in the memory array. However,reduction in memory cell capacitance reduces the electrical signaloutput from the memory cells, making detection of the memory cell outputsignal more difficult. Thus, as the density of DRAM devices increases,it becomes more and more difficult to obtain reasonable storagecapacity.

As DRAM devices are projected as operating in the gigabit range, theability to form such a large number of storage capacitors requiressmaller areas. However, this conflicts with the requirement for largercapacitance because capacitance is proportional to area. Moreover, thetrend for reduction in power supply voltages results in stored chargereduction and leads to degradation of immunity to alpha particle inducedsoft errors, both of which require that the storage capacitance be evenlarger.

In order to meet the high density requirements of VLSI cells in DRAMcells, some manufacturers are utilizing DRAM memory cell designs basedon non-planar capacitor structures, such as complicated stackedcapacitor structures and deep trench capacitor structures. Althoughnon-planar capacitor structures provide increased cell capacitance, sucharrangements create other problems that effect performance of the memorycell. For example, trench capacitors are fabricated in trenches formedin the semiconductor substrate, the problem of trench-to-trench chargeleakage caused by the parasitic transistor effect between adjacenttrenches is enhanced. Moreover, the alpha-particle component of normalbackground radiation can generate hole-electron pairs in the siliconsubstrate which functions as one of the storage plates of the trenchcapacitor. This phenomena will cause a charge stored within the affectedcell capacitor to rapidly dissipate, resulting in a soft error.

Another approach has been to provide DRAM cells having a dynamic gain.These memory cells are commonly referred to as gain cells. For example,U. S. Pat. No. 5,220,530 discloses a two-transistor gain-type dynamicrandom access memory cell. The memory cell includes two field-effecttransistors, one of the transistors functioning as write transistor andthe other transistor functioning as a data storage transistor. Thestorage transistor is capacitively coupled via an insulating layer tothe word line to receive substrate biasing by capacitive coupling fromthe read word line. This gain cell arrangement requires a word line, abit or data line, and a separate power supply line which is adisadvantage, particularly in high density memory structures.

The inventors have previously disclosed a DRAM gain cell using twotransistors. (See generally, L. Forbes, “Merged Transistor Structure forGain Memory Cell,” U.S. Pat. No. 5,732,014, issued 24 Mar. 1998,continuation granted as U.S. Pat. No. 5,897,351, issued 27 Apr. 1999). Anumber of other gain cells have also been disclosed. (See generally,Sunouchi et al., “A self-Amplifying (SEA) Cell for Future High DensityDRAMs,” Ext. Abstracts of IEEE Int. Electron Device Meeting, pp. 465-468(1991); M. Terauchi et al., “A Surrounding Gate Transistor (SGT) GainCell for Ultra High Density DRAMS,” VLSI Tech. Symposium, pp. 21-22(1993); S. Shukuri et al., “Super-Low-Voltage Operation of a Semi-StaticComplementary Gain RAM Memory Cell,” VLSI Tech. Symposium pp. 23-24(1993); S. Shukuri et al., “Super-low-voltage operation of a semi-staticcomplementary gain DRAM memory cell,” Ext. Abs. of IEEE Int. ElectronDevice Meeting, pp. 1006-1009 (1992); S. Shukuri et al., “A Semi-StaticComplementary Gain Cell Technology for Sub-1 V Supply DRAM's,” IEEETrans. on Electron Devices, Vol. 41, pp. 926-931 (1994); H. Wann and C.Hu, “A Capacitorless DRAM Cell on SOI Substrate,” Ext. Abs. IEEE Int.Electron Devices Meeting, pp. 635-638; W. Kim et al., “An ExperimentalHigh-Density DRAM Cell with a Built-in Gain Stage,” IEEE J. ofSolid-State Circuits, Vol. 29, pp. 978-981 (1994); W. H. Krautschneideret al., “Planar Gain Cell for Low Voltage Operation and GigabitMemories,” Proc. VLSI Technology Symposium, pp. 139-140 (1995); D. M.Kenney, “Charge Amplifying trench Memory Cell,” U.S. Pat. No. 4,970,689,13 Nov. 1990; M. Itoh, “Semiconductor memory element and method offabricating the same,” U.S. Pat. No. 5,220,530, 15 Jun. 1993; W. H.Krautschneider et al., “Process for the Manufacture of a high densityCell Array of Gain Memory Cells,” U.S. Pat. No. 5,308,783, 3 May 1994;C. Hu et al., “Capacitorless DRAM device on Silicon on InsulatorSubstrate,” U.S. Pat. No. 5,448,513, 5 Sep. 1995; S. K. Banerjee,“Method of making a Trench DRAM cell with Dynamic Gain,” U.S. Pat. No.5,066,607, 19 Nov. 1991; S. K. Banerjee, “Trench DRAM cell with DynamicGain,” U.S. Pat. No. 4,999,811, 12 Mar. 1991; Lim et al., “Twotransistor DRAM cell,” U.S. Pat. No. 5,122,986, 16 Jun. 1992).

Recently a one transistor gain cell has been reported as shown in FIG.3. (See generally, T. Ohsawa et al., “Memory design using one transistorgain cell on SOI,” IEEE Int. Solid State Circuits Conference, SanFrancisco, 2002, pp. 152-153). FIG. 3 illustrates a portion of a DRAMmemory circuit containing two neighboring gain cells, 301 and 303. Eachgain cell, 301 and 303, is separated from a substrate 305 by a buriedoxide layer 307. The gain cells, 301 and 303, are formed on the buriedoxide 307 and thus have a floating body, 309-1 and 309-2 respectively,separating a source region 311 (shared for the two cells) and a drainregion 313-1 and 313-2. A bit/data line 315 is coupled to the drainregions 313-1 and 313-2 via bit contacts, 317-1 and 317-2. A groundsource 319 is coupled to the source region 311. Wordlines or gates,321-1 and 321-2, oppose the floating body regions 309-1 and 309-2 andare separated therefrom by a gate oxide, 323-1 and 323-2.

In the gain cell shown in FIG. 3 a floating body, 309-1 and 309-2, backgate bias is used to modulate the threshold voltage and consequently theconductivity of the NMOS transistor in each gain cell. The potential ofthe back gate body, 309-1 and 309-2, is made more positive by avalanchebreakdown in the drain regions, 313-1 and 313-2, and collection of theholes generated by the body, 309-1 and 309-2. A more positive potentialor forward bias applied to the body, 309-1 and 309-2, decreases thethreshold voltage and makes the transistor more conductive whenaddressed. Charge storage is accomplished by this additional chargestored on the floating body, 309-1 and 309-2. Reset is accomplished byforward biasing the drain-body n-p junction diode to remove charge fromthe body.

Still, there is a need in the art for a memory cell structure fordynamic random access memory devices, which produces a large amplitudeoutput signal without significantly increasing the size of the memorycell to improve memory densities.

SUMMARY OF THE INVENTION

The above mentioned problems with conventional memories and otherproblems are addressed by the present invention and will be understoodby reading and studying the following specification. A high densityvertical single transistor gain cell is realized for DRAM operation.

In one embodiment of the present invention, a gain cell includes avertical transistor having a source region, a drain region, and afloating body region therebetween. A gate opposes the floating bodyregion and is separated therefrom by a gate oxide on a first side of thevertical transistor. A floating body back gate opposes the floating bodyregion on a second side of the vertical transistor and is separatedtherefrom by a dielectric to form a body capacitor. The floating bodyback gate includes a capacitor plate and forms a capacitor with thefloating body. The capacitor is operable to increase a capacitance ofthe floating body and enables charge storage on the floating body. Thus,the floating body back gate is operable to modulate the thresholdvoltage and conductivity of the vertical transistor.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating conventional dynamic randomaccess memory (DRAM) cells.

FIG. 2 is a block diagram illustrating a DRAM device.

FIG. 3 illustrates a portion of a DRAM memory circuit containing twoneighboring gain cells.

FIG. 4A is a cross-sectional view illustrating an embodiment of a pairof memory cells according to the teachings of the present invention.

FIG. 4B illustrates an electrical equivalent circuit of the pair ofmemory cells shown in FIG. 4A.

FIG. 4C illustrates an embodiment for one mode of operation according tothe teachings of the present invention.

FIG. 4D illustrates another embodiment for a mode of operation accordingto the teachings of the present invention.

FIG. 5 illustrates an embodiment of voltage waveforms used to write dataon to the floating body of a memory cell according to the teachings ofthe present invention.

FIG. 6 is a graph plotting the drain current versus the gate voltage fora memory cell according to the teachings of the present invention.

FIG. 7 is a block diagram illustrating an embodiment of an electronicsystem utilizing the memory cells of the present invention.

FIGS. 8A and 8B illustrate one embodiment of a fabrication technique formemory cells according to the teachings of the present invention.

FIGS. 9A and 9B illustrate another embodiment of a fabrication techniquefor memory cells according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. The embodiments are intended to describeaspects of the invention in sufficient detail to enable those skilled inthe art to practice the invention. Other embodiments may be utilized andchanges may be made without departing from the scope of the presentinvention. In the following description, the terms wafer and substrateare interchangeably used to refer generally to any structure on whichintegrated circuits are formed, and also to such structures duringvarious stages of integrated circuit fabrication. Both terms includedoped and undoped semiconductors, epitaxial layers of a semiconductor ona supporting semiconductor or insulating material, combinations of suchlayers, as well as other such structures that are known in the art.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizonal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

FIG. 4A is a cross-sectional view illustrating an embodiment of a pairof memory cells, 401-1 and 401-2, according to the teachings of thepresent invention. The embodiment of the memory cells, 401-1 and 401-2,in FIG. 4A differ from those shown in FIG. 3 in that the transistors arevertical allowing for a separate body capacitor, 403-1 and 403-2, andbody capacitor plate, 405-1 and 405-2, on one side of the verticaltransistor cells, 401-1 and 401-2.

In the embodiment of FIG. 4A, each gain cell, 401-1 and 401-2, along acolumn of an array is formed on an n+ conductivity type sourceline 407formed on a p-type substrate 409. The vertical transistors 401-1 and401-2 include an n+source region, 411-1 and 411-2 respectively, which insome embodiments is integrally formed with the sourceline 407. In theembodiment of FIG. 4A a p-type conductivity material which serves as thebody regions, 413-1 and 413-2, is formed vertically on the n+sourceregions, 411-1 and 411-2. An n+type conductivity material is formedvertically on the body regions, 413-1 and 413-2, and serves as the drainregions, 415-1 and 415-2. A data/bit line 417 couples to the drainregions, 415-1 and 415-2, along columns of an array. A gate, 419-1 and419-2, is formed on another side of the vertical transistor cells, 401-1and 401-2 from the body capacitor, 403-1 and 403-2, and body capacitorplate, 405-1 and 405-2.

FIG. 4B illustrates an electrical equivalent circuit for the pair ofmemory cells, 401-1 and 401-2 shown in FIG. 4A. In FIG. 4B, wordlines421-1 and 421-2 are shown connected to gates 419-1 and 419-2. Accordingto the teachings of the present invention, the body capacitor, 403-1 and403-2, in each cell, 401-1 and 401-2, increases the capacitance of thefloating body, 413-1 and 413-2, and enables more charge storage.

FIG. 4C shows a single vertical cell, e.g. 401-1 from FIGS. 4A and 4B,and illustrates an embodiment for one mode of operation according to theteachings of the present invention. In the mode of operation, shown inFIG. 4C, the body capacitor plate 405-1 and the source region 411-1 aregrounded. The mode of operation, shown in FIG. 4C, is similar to that ofthe cell shown in FIG. 3. Data, e.g. a one (1) state, is written ontothe cell 401-1 by applying both positive gate 419-1 and drain 415-1voltage causing avalanche breakdown and the body to collect the holeswhich are generated.

FIG. 5 illustrates the voltage waveforms used to write data on to thefloating body. The voltage waveform at the drain is represented at 515and the voltage waveform at the gate is represented at 519. In a firststage 580 to write a first memory state (e.g. “WRITE ONE”), a positivevoltage is applied to both the gate 419-1 and the drain 415-1 causingavalanche breakdown and the body 413-1 to collect the holes which aregenerated. The standby condition 582, or “HOLD” condition, places theword line 421-1 and gate 419-1 at a negative voltage which drives thebody 413-1 to a negative potential by virtue of the capacitive couplingof the body 413-1 to the word line and gate 419-1. In a second stage 584to write a second memory state (e.g. “WRITE ZERO”), the gate 419-1 isdriven positive and the drain 415-1 is driven negative. This actionforward biases the drain 415-1 and body 413-1 junction and removes anystored charge.

The cell 401-1 is read by addressing the word line 421-1 and determiningthe conductivity of the transistor 401-1. If the body 413-1 has storedcharge it will have a more positive potential than normal. The morepositive potential causes the threshold voltage of the transistor 401-1to be lower and the device to conduct more than normal as shown in FIG.6.

FIG. 6 is a graph plotting the drain current I_(DS) versus the gatevoltage V_(GS) for the vertical memory cells of the present invention.FIG. 6 illustrates the difference in transistor current, with smallV_(DS), with and without stored floating body charge. In FIG. 6, thedashed line, represented at 686, represents the second state “zero”stored and the solid line, represented at 688. represents the firststate “one” stored.

FIG. 4D illustrates another embodiment for a mode of operation of thesingle vertical cell, e.g. 401-1 from FIGS. 4A and 4B. In the embodimentof FIG. 4D, the mode of operation is to also allow provisions forbiasing the source line 407 to appositive potential. Biasing thesourceline 407 to a positive potential can be used in conjunction with anegative word line 421-1 voltage to drive the p-type body 413-1 andn-type source and drain, 411-1 and 415-1 respectively, junctions to alarger reverse bias during standby. This insures the floating body 413-1will not become forward biased during standby. Thus, stored charge willnot be lost due to leakage currents with forward bias.

FIG. 7 is a block diagram of a processor-based system 700 utilizingsingle transistor vertical memory gain cells constructed in accordancewith the present invention. That is, the system 700 utilizes the memorycell illustrated in FIGS. 4A-4D. The processor-based system 700 may be acomputer system, a process control system or any other system employinga processor and associated memory. The system 700 includes a centralprocessing unit (CPU) 702, e.g., a microprocessor, that communicateswith the RAM 712 and an I/O device 708 over a bus 720. It must be notedthat the bus 720 may be a series of buses and bridges commonly used in aprocessor-based system, but for convenience purposes only, the bus 720has been illustrated as a single bus. A second I/O device 710 isillustrated, but is not necessary to practice the invention. Theprocessor-based system 700 also includes read-only memory (ROM) 714 andmay include peripheral devices such as a floppy disk drive 704 and acompact disk (CD) ROM drive 706 that also communicates with the CPU 702over the bus 720 as is well known in the art.

It should be noted that the memory state stored on the floating bodyback gate can be determined as a separate operation by measuringindependently the threshold voltage of the transfer devices.

It will be appreciated by those skilled in the art that additionalcircuitry and control signals can be provided, and that the memorydevice 700 has been simplified to help focus on the invention.

It will be understood that the embodiment shown in FIG. 7 illustrates anembodiment for electronic system circuitry in which the novel memorycells of the present invention are used. The illustration of system 701,as shown in FIG. 7, is intended to provide a general understanding ofone application for the structure and circuitry of the presentinvention, and is not intended to serve as a complete description of allthe elements and features of an electronic system using the novel memorycell structures. Further, the invention is equally applicable to anysize and type of system 700 using the novel memory cells of the presentinvention and is not intended to be limited to that described above. Asone of ordinary skill in the art will understand, such an electronicsystem can be fabricated in single-package processing units, or even ona single semiconductor chip, in order to reduce the communication timebetween the processor and the memory device.

Applications containing the novel memory cell of the present inventionas described in this disclosure include electronic systems for use inmemory modules, device drivers, power modules, communication modems,processor modules, and application-specific modules, and may includemultilayer, multichip modules. Such circuitry can further be asubcomponent of a variety of electronic systems, such as a clock, atelevision, a cell phone, a personal computer, an automobile, anindustrial control system, an aircraft, and others.

Methods of Fabrication

The inventors have previously disclosed a variety of vertical devicesand applications employing transistors along the sides of rows or finsetched into bulk silicon or silicon on insulator wafers for devices inarray type applications in memories. (See generally, U.S. Pat. Nos.6,072,209; 6,150,687; 5,936,274 and 6,143,636; 5,973,356 and 6,238,976;5,991,225 and 6,153,468; 6,124,729; 6,097,065). The present inventionuses similar techniques to fabricate the single transistor verticalmemory gain cell described herein. Each of the above reference USPatents is incorporated in full herein by reference.

FIG. 8A outlines one embodiment of a fabrication technique for theembodiment illustrated in FIG. 4C. In FIG. 8A, a p-type substrate 801has been processed to include layers thereon of an n+ conductivity type803, a p conductivity type 804, and another n+ conductivity type 805. Inthe embodiment of FIG. 8A, the fabrication continues with the waferbeing oxidized and then a silicon nitride layer (not shown) is depositedto act as an etch mask for an anisotropic or directional silicon etchwhich will follow. This nitride mask and underlying oxide are patternedand trenches are etched as shown in both directions leaving blocks ofsilicon, e.g. 807-1, 807-2, 807-3, and 807-4, having alternating layersof n and p type conductivity material. Any number of such blocks can beformed on the wafer.

In FIG. 8B, the fabrication has continued with both trenches beingfilled with oxide 808 and the whole structure planarized by CMP. Oxideis then removed from the trenches, e.g. 809, for the eventual word lineand capacitor plate formation. The remaining structure as shown can berealized by conventional techniques including gate oxidation anddeposition and anisotropic etch of polysilicon along the sidewalls toform body capacitor and word lines. The data or bit lines on top can berealized using conventional metallurgy.

FIG. 9A outlines one embodiment of a fabrication technique for theembodiment illustrated in FIG. 4D. In FIG. 9A, a p-type substrate 901has been processed to include layers thereon of an n+conductivity type903, a p conductivity type 904, and another n+ conductivity type 905. Inthe embodiment of FIG. 9A, the fabrication continues with the waferbeing oxidized and then a silicon nitride layer (not shown) is depositedto act as an etch mask for an anisotropic or directional silicon etchwhich will follow. This nitride mask and underlying oxide are patternedand trenches are etched as shown in both directions leaving blocks ofsilicon, e.g. 907-1, 907-2, 907-3, and 907-4, having alternating layersof n and p type conductivity material. Any number of such blocks can beformed on the wafer.

In the embodiment of FIG. 9A, two masking steps are used and one set oftrenches, e.g. trench 910, is made deeper than the other, e.g. trench909, in order to provide separation and isolation of the source lines903. As before, both trenches are filled with oxide and the wholestructure planarized by CMP. The remaining fabrication proceeds aspreviously described and will result in devices with the equivalentcircuit shown in FIG. 4D.

While the description here has been given for a p-type substrate, analternative embodiment would work equally well with n-type orsilicon-on-insulator substrates. In that case, the sense transistorwould be a PMOS transistor with an n-type floating body.

CONCLUSION

The cell can provide a very high gain and amplification of the storedcharge on the floating body of the NMOS sense transistor. A small changein the threshold voltage caused by charge stored on the floating bodywill result in a large difference in the number of holes conductedbetween the drain and source of the NMOS sense transistor during theread data operation. This amplification allows the small storagecapacitance of the sense amplifier floating body to be used instead of alarge stacked capacitor storage capacitance. The resulting cell has avery high density with a cell area of 4F², where F is the minimumfeature size, and whose vertical extent is far less than the totalheight of a stacked capacitor or trench capacitor cell and accesstransistor.

It is to be understood that the above description is intended to beillustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reviewing the abovedescription. The scope of the invention should, therefore, be determinedwith reference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

1. A device, comprising: a vertical transistor having a source region, adrain region, and a body region therebetween, and further having a firstside and a second side; a gate opposing the body region on the firstside of the vertical transistor; and a floating body back gate opposingthe body region on the second side of the vertical transistor, whereinthe floating body back gate has a thickness approximately equal to thethickness of the gate, wherein the gate is connected to a word line toselectively provide the gate with at least a first word line potentialand a second word line potential during memory cell operation, the drainregion is connected to a bit line to selectively provide the drainregion with at least a first bit line potential and a second bit linepotential during memory cell operation, the source region is connectedto a source line to selectively provide the source region with at leasta first source line potential and a second source line potential duringmemory cell operation, and a fixed potential is applied to the floatingbody back gate during memory cell operation.
 2. The device of claim 1,including a memory cell, wherein the memory cell comprises the verticaltransistor, the gate and the floating body back gate.
 3. The device ofclaim 2, wherein the memory cell includes a single transistor memorygain cell.
 4. The device of claim 2, wherein, for a minimum feature sizeF, the memory cell has a cell area of 4F².
 5. The device of claim 1,including a memory array, the memory cell including the verticaltransistor having the source region, the drain region, and the bodyregion therebetween, the gate, and the floating body back gate.
 6. Thedevice of claim 5, including an electronic system, the electronic systemcomprising a processor and a memory coupled to the processor, whereinthe memory includes the memory array.
 7. A memory cell, comprising: avertical transistor having a source region, a drain region, and a bodyregion therebetween; a gate opposing the body region and separatedtherefrom by a gate oxide on a first side of the vertical transistor;and a floating body back gate opposing the body region on a second sideof the vertical transistor, wherein the floating body back gate has athickness approximately equal to the thickness of the gate, wherein thegate is connected to a word line to selectively provide the gate with atleast a first word line potential and a second word line potentialduring memory cell operation, the drain region is connected to a bitline to selectively provide the drain region with at least a first bitline potential and a second bit line potential during memory celloperation, the source region is connected to a source line toselectively provide the source region with at least a first source linepotential and a second source line potential during memory celloperation, and a fixed potential is applied to the floating body backgate during memory cell operation.
 8. The memory cell of claim 7,wherein the floating body back gate is used to modulate the thresholdvoltage and conductivity of the vertical transistor.
 9. The memory cellof claim 7, wherein the body region of the vertical transistor is afloating body.
 10. The memory cell of claim 9, wherein the floating bodyback gate is a capacitor plate and forms a capacitor with the floatingbody.
 11. The memory cell of claim 10, wherein the capacitor is operableto increase a capacitance of the floating body and enables chargestorage on the floating body.
 12. A single transistor memory gain cell,comprising: a vertical transistor having a source region, a drainregion, and a floating body region therebetween; a gate opposing thefloating body region and separated therefrom by a gate oxide on a firstside of the vertical transistor; a floating body back gate opposing thebody region on a second side of the vertical transistor, wherein thefloating body back gate is used to modulate the threshold voltage andconductivity of the vertical transistor, and wherein the floating bodyback gate has a thickness approximately equal to the thickness of thegate, wherein the gate is connected to a word line to selectivelyprovide the gate with at least a first word line potential and a secondword line potential during memory cell operation, the drain region isconnected to a bit line to selectively provide the drain region with atleast a first bit line potential and a second bit line potential duringmemory cell operation, the source region is connected to a source lineto selectively provide the source region with at least a first sourceline potential and a second source line potential during memory celloperation, and a fixed potential is applied to the floating body backgate during memory cell operation.
 13. The memory gain cell of claim 12,wherein the floating body back gate is a capacitor plate and forms acapacitor with the floating body.
 14. The memory gain cell of claim 13,wherein the capacitor is operable to increase a capacitance of thefloating body and enables charge storage on the floating body.
 15. Thememory gain cell of claim 12, wherein the vertical transistor is ap-channel MOS transistor (PMOS).
 16. The memory gain cell of claim 12,wherein the memory gain cell is a dynamic random access memory (DRAM)cell.
 17. A Memory array, comprising: a number of vertical transistorsformed on a substrate, wherein each vertical transistor includes; asource region; a drain region; a floating body region formed verticallybetween the source and drain region, wherein the floating body regionoperable to store a charge; a gate opposing the floating body region andseparated therefrom by a gate oxide on a first side of each verticaltransistor; and a floating body back gate opposing the floating bodyregion on a second side of the vertical transistor, wherein the floatingbody back gate has a thickness approximately equal to the thickness ofthe gate, a number of bitlines coupled to the drain regions alongcolumns in the array, wherein of bitlines coupled to the drain regionsalong columns in the array, provide the gate with at least a first wordline potential and a second word line potential during memory celloperation, the drain region is connected to one of the bit lines toselectively provide the drain region with at least a first bit linepotential and a second bit line potential during memory cell operation,the source region is connected to a source line to selectively providethe source region with at least a first source line potential and asecond source line potential during memory cell operation, and a fixedpotential is applied to the floating body back gate during memory celloperation.
 18. The memory array of claim 17, wherein the gate and thefloating body back gate are formed on opposite sides of each verticaltransistor.
 19. The memory array of claim 17, wherein the array furtherincludes a number of sourcelines, wherein the source region of eachvertical transistor is coupled to a souceline along columns in thearray.
 20. The memory array of claim 17, wherein in each verticaltransistor the floating body back gate is operable to modulate athreshold voltage and a conductivity of the vertical transistor.
 21. Thememory array of claim 17, wherein in each vetical transistor thefloating body back gate is a capacitor plate and forms a body capacitorwith the floating body.
 22. The memory array of claim 21, wherein thebody capacitor is operable to increase a capacitance of the floatingbody and enables charge storage on the floating body.
 23. The memoryarray of claim 17, wherein the memory array is included in a dynamicrandom access memory (DRAM) chip.
 24. An electronic system, comprising:a processor; and a memory operably coupled to the processor, wherein thememory includes a memory array having; a number of vertical transistors,wherein each vertical transistor includes: a source region; a drainregion; a floating body region formed vertically between the source anddrain region, wherein the floating body region operable to store acharge; a gate opposing the floating body region and separated therefromby a gate oxide on a first side of each vertical transistor; and afloating body back gate opposing the floating body region on a secondside of the vertical transistor, wherein the floating body back gate hasa thickness approximately equal to the thickness of the gate, a numberof bitlines coupled to the drain regions along columns in the array,wherein of bitlines coupled to the drain regions along columns in thearray, provide the gate with at least a first word line potential and asecond word line potential during memory cell operation, the drainregion is connected to one of the bit lines to selectively provide thedrain region with at least a first bit line potential and a second bitline potential during memory cell operation, the source region isconnected to a source line to selectively provide the source region withat least a first source line potential and a second source linepotential during memory cell operation, and a fixed potential is appliedto the floating body back gate during memory cell operation.
 25. Thesystem of claim 24, wherein the gate and the floating body back gate areformed on opposite sides of each vertical transistor.
 26. The system ofclaim 24, wherein the memory array further includes a number ofsourcelines, wherein the source region of each vertical transistor iscoupled to a sourceline along columns in the memory array.
 27. Thesystem of claim 24, wherein in each vertical transistor the floatingbody back gate is operable to modulate a threshold voltage and aconductivity of the vertical transistor.
 28. The system of claim 24,wherein in each vertical transistor the floating body back gate is acapacitor plate and forms a body capacitor with the floating body. 29.The system of claim 28, wherein the body capacitor is operable toincrease a capacitance of the floating body and enables charge storageon the floating body.
 30. The system of claim 24, wherein the memoryarray is included in a dynamic random access memory (DRAM) chip.
 31. Thesystem of claim 24, wherein the processor and memory are formed on asingle chip.
 32. A memory cell, comprising: a vertical transistor havinga source region, a drain region, and a floating body regiontherebetween; a gate operably positioned with respect to the floatingbody region on a first side of the vertical transistor; and a bodycapacitor plate operably positioned with respect to the floating bodyregion on a second side of the vertical transistor, wherein the bodycapacitor plate has a thickness approximately equal to the thickness ofthe gate, wherein, for a minimum feature size F, the memory cell has acell area of 4F², wherein the gate is connected to a word line toselectively provide the gate with at least a first word line potentialand a second word line potential during memory cell operation, the drainregion is connected to a bit line to selectively provide the drainregion with at least a first bit line potential and a second bit linepotential during memory cell operation, the source region is connectedto a source line to selectively provide the source region with at leasta first source line potential and a second source line potential duringmemory cell operation, and a fixed potential is applied to the floatingbody back gate during memory cell operation.
 33. The memory cell ofclaim 32, wherein the body capacitor plate forms a capacitor with thefloating body region to enhance charge storage in the floating bodyregion.
 34. A memory array, comprising: a number of memory cells, eachmemory cell having a cell area of 4F² for a minimum feature size F, eachmemory cell comprising a vertical transistor, including: a sourceregion; a drain region; a floating body region formed vertically betweenthe source and drain region; a gate opposing the floating body region ona first side of each vertical transistor; and a body capacitor plateopposing the floating body region on a second side of the verticaltransistor to form a capacitor with the floating body region to enhancecharge storage in the floating body region, wherein the body capacitorplate has a thickness approximately equal to the thickness of the gate,a number of bitlines coupled to the drain regions along columns in thearray, wherein the gate is connected to a word line to selectivelyprovide the gate with at least a first word line potential and a secondword line potential during memory cell operation, the drain region isconnected to a bit line to selectively provide the drain region with atleast a first bit line potential and a second bit line potential duringmemory cell operation, the source region is connected to a source lineto selectively provide the source region with at least a first sourceline potential and a second source line potential during memory celloperation, and a fixed potential is applied to the floating body backgate during memory cell operation.
 35. A memory cell, comprising: avertical transistor having a source region, a drain region, and afloating body region therebetween; a gate opposing the floating bodyregion and separated therefrom by a gate oxide on a first side of thevertical transistor; and means for modulating a threshold voltage and aconductivity of the vertical transistor, wherein the means formodulating includes a floating body back gate opposing the floating bodyregion on a second side of the vertical transistor, wherein the floatingbody back gate has a thickness approximately equal to the thickness ofthe gate, wherein the gate is connected to a word line to selectivelyprovide the gate with at least a first word line potential and a secondword line potential during memory cell operation, the drain region isconnected to a bit line to selectively provide the drain region with atleast a first bit line potential and a second bit line potential duringmemory cell operation, and the source region is connected to a sourceline to selectively provide the source region with at least a firstsource line potential and a second source line potential during memorycell operation and a fixed potential is applied to the floating bodyback gate during memory cell operation.
 36. The memory cell of claim 35,wherein the means for modulating includes storing and removing a chargein the floating body region of the vertical transistor.
 37. The memorycell of claim 35, wherein means for modulating includes increasing acapacitance of the floating body region of the vertical transistor. 38.The memory cell of claim 35, wherein the vertical transistor is ann-channel MOS transistor (NMOS).
 39. The memory cell of claim 35,wherein the memory cell is a dynamic random access memory (DRAM) cell.